1. Field of the Invention
An embodiment of the present invention relates to microelectronic device fabrication. In particular, an embodiment of the present invention relates to a tantalum containing adhesion layer for metal contacts deposited by atomic layer deposition to minimize contact resistance and maximize the low resistance conductive material within the contact.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. These transistors are generally connected to one another or to devices external to the microelectronic device by conductive traces and contacts through which electronic signals are sent and/or received.
One process used to form contacts is known as a “damascene process”. In a typical damascene, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a hole extending to a source or drain of an underlying transistor. The photoresist material is then removed (typically by an oxygen plasma) and an adhesion layer may be deposit within the hole to prevent delimination between the dielelctric material and a subsequently deposited conductive material. The hole is then filled, usually by deposition, with the conductive material (e.g., such as metal and metal alloys thereof). For example, a 60-90 angstrom thick titanium nitride adhesion layer may be deposited in about a 70-80 nm diameter hole (65 nm technology node) by chemical vapor deposition followed by the filling of the remainder of the hole with tungsten. The adhesion layer may also prevent damage to the dielectric material during the deposition of the conductive material. For example, a titanium nitride adhesion layer prevents damage to the dielectric layer (such as silicon dioxide) by a tungsten hexafluoride gas used to deposit tungsten, as will be understood to those skilled in the art. The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes the conductive material and adhesion layer that is not within the hole from the surface of the dielectric material, to form the contact.
It is, of course, understood that since the adhesion layer has a higher electrical resistance than the conductive material, the conductive material must have a sufficient cross-sectional area within the contact to effectively conduct signals. However, as transistors become smaller with each successive technology node, the contact geometries decrease (i.e., “scale down”). Thus, a 60-90 angstrom thick adhesion layer, discussed above, will become problematical. For example, at the 45 nm technology node, the contact geometry (i.e., width) will be about 60 nm. Thus, a 90 angstrom thick adhesion layer will occupy about 30% of the contact width. As a further example, at the 30 nm technology node, the contact geometry will be about 40 nm. Thus, a 90 angstrom thick adhesion layer will occupy about 45% of the contact width. With both of these examples, it will be clear to those skilled in the art that the remaining contact width will likely not yield a cross-sectional area of the conductive material within the contact that will be sufficient to effectively conduct a reliable signal.
Therefore, it would be advantageous to develop apparatus and techniques to form an adhesion layer which will allow effective scaling down of contacts, as transistors become smaller with each successive technology node.